Galois field polynomial multiply/divide circuits are well known in the art. In such a circuit, it is desired to multiply or divide a first plurality of binary signals by a second plurality of binary signals. Galois field multiply/divide circuits are used to calculate CRC (Cyclic Redundancy Check) bit signals in communications, as well as convolution encoding signals, among other applications.
In a typical prior art Galois field multiply/divide circuit, shift registers are used to accomplish the operation. In a typical prior art Galois field multiply circuit, a plurality of shift registers with adders and multipliers are used to accomplish the operation. In the prior art Galois field multiply circuit, each bit of a first plurality of binary signals is shifted into a shift register, multiplied by the plurality of second binary signals, added, and so forth. Hence, the operation is "serial" in nature in that at least N+1 number of clock cycles are required to accomplish the multiplication operation where N is the number of bits of the first plurality of binary signals.
Similarly, in a typical prior art Galois field divide circuit, shift registers and adders and multipliers are used to accomplish the operation. The number of shifts or cycles that is required to accomplish the operation is equal to the degree of the data of the polynomial plus 1. Again, similar to the prior art Galois field multiply circuit, the prior art Galois field divide circuit is "serial" in nature.
See, e.g. U.S. Pat. No. 5,341,322, for an example of a prior art divide circuit and U.S. Pat. No. 5,270,962 for an example of a prior art multiply/divide circuit.